Download PCI Bus Demystified, Second Edition (Demystifying Technology by Doug Abbott PDF

By Doug Abbott

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Extra resources for PCI Bus Demystified, Second Edition (Demystifying Technology Series)

Sample text

All PCI agents are required to generate even parity on the AD and C/BE lines. With two exceptions, all agents are required to have the ability to check parity whether or not they choose to take any action in response to a detected parity error. Parity errors during data phases are reported on the PERR# line. The SERR# line is used to report parity errors during address phases and Special Cycle transactions. It can also be used to report other system errors. SERR# is considered to be a fatal condition.

This is the first read data phase and also a turnaround cycle for PAR. 5 Target places computed parity on PAR. Otherwise, this is an idle cycle. 38 Bus Protocol 6 Initiator reports any parity error here by asserting PERR#. This also happens to be the address phase for the next transaction. Clocks 7 to 9 illustrate the same process for write transactions. Note that no turnaround is required on either AD or PAR. Also note that because SERR# is open-drain, it may require more than one clock cycle to return to the non-asserted state.

When the end of the cache line is reached, the address wraps around to the beginning of the cache line until the entire line has been transferred. If the burst continues beyond this point, the next transfer is to/from the same location in the next cache line where the transfer began. Table 3-2: AD[1:0] for memory transfers. AD1 AD0 Address Sequence 0 0 Linear (sequential) addressing. Target increments address by 4 after each data phase. 0 1 Reserved. Target disconnects after first data phase. 1 0 Cache line wrap.

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